The Developer’s Suite is based on 25 years of development and continuous improvement arising from valuable customer feedback. When used together with Intel’s design tools, the Developer’s Suite provides a market-unique solution that can achieve unmatched development productivity. The Gidel Developer’s Suite includes the following components:
Gidel Proc Developer’s Kit is a set of building blocks designed for maximum performance and fast, high-productivity system development. The kit includes the ProcWizard application, supporting libraries, and Gidel IPs.
Gidel ProcWizard™, included in the Proc Developer’s Kit, is a hardware–software integration application that simplifies project development tasks. Working in conjunction with Gidel FPGA boards, ProcWizard enables users to rapidly build a design that may be automatically translated into HDL and C++ code. The generated C++ code communicates with the generated HDL design via the PCI/e bus to ensure easy hardware–software integration.
In addition to code generation, the ProcWizard enables developers to test and debug designs in the PC environment. While in ProcWizard Debug Mode, designers can access the Proc board on-the-fly with a structural browser, manually or using macros/scripts.
Gidel ProcWizard enables hardware and software designers to work in parallel, sharing the same information and project definitions. This way, the time-to-market of project development may be greatly reduced and product reliability and maintenance may be improved.
The Gidel Developer’s kit includes a set of IPs for simplifying and enhancing development tasks.
The MultiPort IP is a unique memory controller that optimizes on-board memory according to application data flow needs. This controller enables parallel access from up to 16 totally independent ports per memory bank. Each port may belong to a separate logical memory. All ports are connected to the same memory domain and can be accessed independently or simultaneously, with individual clock domains and data widths.
The MegaFIFO provides a simple and convenient way to transfer data between the acceleration board’s large memory banks and the FPGA logic and/or the host.
The MegaDelay IP provides a convenient and effective method to create high-bandwidth large delays for optimized streaming applications. This IP, combined with the FPGA’s internal memory and logic, may significantly reduce memory access requirements.