{"id":1160,"date":"2017-11-09T17:41:00","date_gmt":"2017-11-09T17:41:00","guid":{"rendered":"https:\/\/gidel.com\/?p=1160"},"modified":"2026-09-20T20:02:33","modified_gmt":"2026-09-20T20:02:33","slug":"fpga-acceleration-chrec-supercomputer","status":"publish","type":"post","link":"https:\/\/gidel.com\/fpga-acceleration-chrec-supercomputer\/","title":{"rendered":"CHREC Reconfigurable Supercomputer Powered by Gidel FPGA Acceleration"},"content":{"rendered":"

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FPGA Acceleration in a Reconfigurable Supercomputer<\/strong><\/span><\/h2>\n

A reconfigurable supercomputer can address demanding HPC workloads by combining programmable FPGA processing with scalable high-speed connectivity. At the same time, data centers face exponential data growth and increasing power demands, while traditional CPU-based architectures can require substantial increases in power and cooling as workloads scale. Gidel\u2019s FPGA acceleration technology provides an alternative architecture based on massive parallelism and direct high-speed FPGA connectivity.<\/p>\n

In addition, Gidel\u2019s direct FPGA connectivity allowed FPGA nodes to communicate without routing inter-FPGA data through the host CPU. This architecture supported advanced topologies such as 3D and 12D Torus, and 6D or 24D Hypercube configurations. As a result,<\/strong> the architecture enabled scalable communication for HPC workloads that require high throughput and low latency.<\/p>\n

CHREC Builds a Reconfigurable Supercomputer Using Gidel FPGA Boards<\/h2>\n

The Center for High-Performance Reconfigurable Computing (CHREC), funded by the National Science Foundation, set out to create the fastest research-focused reconfigurable supercomputer in the world. Their goal was to evaluate architectures that deliver both high performance and low energy consumption.<\/p>\n

Initially, CHREC researchers explored CPU-socket accelerators but encountered instability, high costs, and under-performing I\/O bandwidth. They shifted toward PCIe FPGA boards and evaluated multiple vendors. After extensive testing, CHREC selected Gidel for its performance, stability, and superior technical support.<\/p>\n

\n\n\n\n\n\n\n\n\n\n\n\n\n
Novo-G Reconfigurable Supercomputer Architecture<\/caption>\n
Architecture<\/strong><\/th>\nNovo-G Configuration<\/strong><\/th>\n<\/tr>\n<\/thead>\n
Computing Approach<\/strong><\/td>\nFPGA-based reconfigurable computing<\/td>\n<\/tr>\n
Research Organization<\/strong><\/td>\nCenter for High Performance Reconfigurable Computing (CHREC)<\/td>\n<\/tr>\n
Gidel FPGA Platforms<\/strong><\/td>\nPROCStar-III, PROCStar-IV, and ProceV D8<\/td>\n<\/tr>\n
FPGA Interconnect<\/strong><\/td>\nDirect FPGA-to-FPGA links<\/td>\n<\/tr>\n
Network Architecture<\/strong><\/td>\nScalable multi-dimensional topology, including 3D torus configurations<\/td>\n<\/tr>\n
Host Involvement<\/strong><\/td>\nInter-FPGA communication can occur without routing data through the host CPU<\/td>\n<\/tr>\n
Primary Use<\/strong><\/td>\nHPC acceleration, reconfigurable-computing research, and large-scale FPGA application development<\/td>\n<\/tr>\n
Key Architectural Benefit<\/strong><\/td>\nScalable low-latency communication between FPGA nodes<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n
Swipe horizontally to view all columns \u2192<\/div>\n

Why Gidel Was Chosen for the Novo-G Supercomputer<\/h2>\n