{"id":975,"date":"2018-06-21T15:20:00","date_gmt":"2018-06-21T15:20:00","guid":{"rendered":"https:\/\/gidel.com\/?p=975"},"modified":"2026-09-20T20:02:47","modified_gmt":"2026-09-20T20:02:47","slug":"fpga-reversible-compression-ip","status":"publish","type":"post","link":"https:\/\/gidel.com\/fpga-reversible-compression-ip\/","title":{"rendered":"Gidel Launches New Real-Time FPGA Lossless Encoder"},"content":{"rendered":"

FPGA Lossless Encoder for Real-Time Data Processing<\/strong><\/span><\/h2>\n

Gidel\u2019s FPGA Lossless Encoder delivers real-time 1 GB\/s encoding while using a very small FPGA footprint and consuming under 0.2 W. The mathematically reversible compression preserves the original data for exact reconstruction while reducing storage requirements by more than 50%.<\/p>\n

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Why FPGA-Based Reversible Compression Matters Today<\/h2>\n

High-bandwidth imaging, HPC, and sensor systems increasingly generate more data than storage, memory, and host interfaces can handle efficiently. Reversible compression helps reduce this data volume without losing information, making it valuable when every original bit must remain recoverable.<\/p>\n

Implementing compression in the FPGA allows the system to reduce data earlier in the processing path, before it reaches host memory or storage. This can lower downstream bandwidth requirements, reduce storage demand, and preserve CPU resources for other processing tasks.<\/p>\n

Real-Time Lossless Compression in FPGA Hardware<\/h3>\n

Gidel\u2019s reversible compression core runs directly in FPGA hardware as part of the real-time data path. Because the compression engine uses dedicated FPGA logic, it can process incoming data continuously without relying on host software or CPU scheduling.<\/p>\n

In the referenced implementation, the core achieved real-time encoding at 1 GB\/s while using only a very small portion of the FPGA. The compression is mathematically reversible, so the system can reconstruct the original data exactly with zero degradation.<\/p>\n

Gidel\u2019s imaging platforms can combine the FPGA Lossless Encoder with acquisition from typical GigE Vision cameras<\/a>, typical CoaXPress cameras<\/a>, typical Camera Link cameras<\/a>, and user-defined protocols.<\/p>\n

\n\n\n\n\n\n\n\n\n\n\n\n
FPGA Lossless Encoder vs CPU Software Compression<\/caption>\n
Architecture<\/strong><\/th>\nFPGA Lossless Encoder<\/th>\nCPU Software Compression<\/strong><\/th>\n<\/tr>\n<\/thead>\n
Processing Location<\/strong><\/td>\nRuns directly in dedicated FPGA logic within the real-time data path<\/td>\nRuns on the host CPU through software<\/td>\n<\/tr>\n
Streaming Processing<\/strong><\/td>\nProcesses incoming data continuously in a dedicated hardware pipeline<\/td>\nUses general-purpose CPU resources and software execution<\/td>\n<\/tr>\n
Host Data Transfer<\/strong><\/td>\nCan compress data before the system transfers it to host memory or storage<\/td>\nUncompressed data normally reaches host memory before software compression<\/td>\n<\/tr>\n
CPU Load<\/strong><\/td>\nDedicated FPGA logic performs the compression<\/td>\nCompression consumes host CPU processing resources<\/td>\n<\/tr>\n
Integration<\/strong><\/td>\nEngineers can combine compression with acquisition, buffering, preprocessing, and other FPGA functions<\/td>\nCompression operates within the host software workflow<\/td>\n<\/tr>\n
Determinism<\/strong><\/td>\nDedicated hardware provides a fixed real-time processing pipeline<\/td>\nPerformance depends on software execution and available CPU resources<\/td>\n<\/tr>\n
Best Fit<\/strong><\/td>\nContinuous high-bandwidth data streams, imaging, sensors, and embedded acquisition systems<\/td>\nFlexible host-based workflows where software processing is appropriate<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n
Swipe horizontally to view all columns \u2192<\/div>\n

Ultra-Efficient FPGA Lossless Encoder Design<\/h2>\n

The Gidel FPGA reversible compression core uses only a small amount of FPGA logic and consumes less than 0.2 W. In the referenced HawkEye Arria 10-480 implementation, the complete IP occupies approximately 1% of the FPGA resources. This compact footprint makes the core well suited for integration into Gidel FPGA platforms where logic, power, and bandwidth efficiency are critical.<\/p>\n

Real-time reversible compression can also improve system efficiency beyond storage reduction. By compressing data before host transfer or recording, the system can reduce memory traffic, PCIe bandwidth, and SSD storage requirements. As a result, engineers can preserve more system bandwidth for acquisition, processing, and other real-time functions.<\/p>\n

Supported FPGA Platforms<\/h2>\n

Gidel\u2019s FPGA Lossless Encoder can be integrated across Gidel FPGA platforms, including PCIe frame grabbers, Mini FPGA Modules, FantoVision Edge AI systems, and FPGA compute accelerators. These platforms use Altera FPGA<\/a> technology and provide the FPGA resources, memory architecture, and high-bandwidth interfaces required for real-time acquisition, processing, and compression.<\/p>\n

Depending on the platform and system architecture, engineers can place the lossless encoder directly in the FPGA data path alongside acquisition, buffering, preprocessing, and other real-time functions. This allows compressed data to reach host memory or storage earlier in the pipeline, reducing downstream bandwidth and storage requirements.<\/p>\n

Gidel supports its FPGA Lossless Encoder across several FPGA platforms, including:<\/strong><\/p>\n