{"id":988,"date":"2018-11-06T15:50:00","date_gmt":"2018-11-06T15:50:00","guid":{"rendered":"https:\/\/gidel.com\/?p=988"},"modified":"2026-09-20T20:02:57","modified_gmt":"2026-09-20T20:02:57","slug":"jpeg-fpga-compression-ip","status":"publish","type":"post","link":"https:\/\/gidel.com\/jpeg-fpga-compression-ip\/","title":{"rendered":"Gidel Introduces New FPGA JPEG Compression IP"},"content":{"rendered":"

JPEG FPGA Compression IP for Real-Time Imaging<\/h2>\n

Gidel\u2019s FPGA JPEG Compression IP delivers real-time encoding with very low latency, compact FPGA resource usage, and 4\u00d7 higher throughput utilization than comparable solutions. Designed for high-speed Imaging & Vision systems, it processes image data directly in the FPGA path, reducing the amount of data that must be transferred, stored, or handled downstream.<\/p>\n

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High-Speed FPGA Image Compression<\/h2>\n

Gidel, a long-time leader in FPGA-based Vision and Imaging solutions, has introduced a new real-time JPEG encoder for high-speed and embedded imaging systems. The architecture combines compact FPGA resource usage with high processing performance and supports very wide images, making it suitable for demanding high-resolution pipelines.<\/p>\n

The encoder processes image data directly on the FPGA and supports selectable quality settings, allowing customers to balance image quality, bandwidth, and storage requirements. It accepts YCbCr input, with optional conversion from RGB, Bayer, or monochrome formats.<\/p>\n

Designed for High-Bandwidth Imaging Applications<\/h3>\n

The Gidel JPEG Encoder on FPGA<\/strong><\/a> targets applications that require real-time compression at high pixel rates. Typical applications include large-format cameras, multi-camera systems, recording systems, broadcasting, surveillance, smart cities, embedded vision, and other high-bandwidth imaging systems.<\/p>\n

For high-bandwidth camera systems, engineers can implement JPEG compression in the FPGA close to the image source. When engineers integrate the FPGA into a camera or embedded imaging platform, compression can reduce the amount of image data transferred downstream. When an FPGA frame grabber performs JPEG compression after camera acquisition, it can reduce PCIe bandwidth, memory traffic, storage requirements, and host CPU\/GPU load while maintaining a real-time FPGA processing pipeline.<\/p>\n

Gidel\u2019s imaging platforms can combine JPEG compression with acquisition from standard GigE Vision cameras<\/a>, standard CoaXPress cameras<\/a>, standard Camera Link cameras<\/a>, and user-defined protocols.<\/p>\n

FPGA Compression vs CPU and GPU Compression<\/h2>\n

The location of the JPEG encoder in the imaging architecture affects when image data is compressed and how much uncompressed data must move through the rest of the system. FPGA compression can operate directly in the acquisition and image-processing path before the system transfers the data to host memory.<\/p>\n

\n\n\n\n\n\n\n\n\n\n\n
FPGA JPEG Compression vs CPU and GPU Compression<\/caption>\n
Architecture<\/strong><\/th>\nFPGA JPEG Compression<\/strong><\/th>\nCPU Compression<\/strong><\/th>\nGPU Compression<\/strong><\/th>\n<\/tr>\n<\/thead>\n
Processing Location<\/strong><\/td>\nThe FPGA can process and compress image data directly in the acquisition path<\/td>\nThe host CPU performs the compression<\/td>\nThe GPU compresses the image after the system transfers the data to GPU-accessible memory<\/td>\n<\/tr>\n
Streaming Processing<\/strong><\/td>\nDedicated hardware pipeline can process image data continuously as it arrives<\/td>\nSoftware processing on general-purpose CPU resources<\/td>\nParallel software processing using GPU resources<\/td>\n<\/tr>\n
Uncompressed Host Transfer<\/strong><\/td>\nThe FPGA can compress image data before the system transfers it to the host<\/td>\nImage data normally reaches host memory before CPU compression<\/td>\nThe system must transfer image data to GPU-accessible memory before the GPU processes it<\/td>\n<\/tr>\n
Host CPU Load<\/strong><\/td>\nDedicated FPGA logic performs the JPEG encoding<\/td>\nJPEG encoding uses CPU processing resources<\/td>\nThe GPU handles the JPEG processing instead of the CPU<\/td>\n<\/tr>\n
Integration with Acquisition<\/strong><\/td>\nEngineers can integrate compression with acquisition, buffering, ISP, ROI, and other FPGA processing<\/td>\nThe host software pipeline performs compression after acquisition<\/td>\nThe host\/GPU processing pipeline handles the compression<\/td>\n<\/tr>\n
System Benefit<\/strong><\/td>\nThe FPGA can reduce downstream PCIe, memory, storage, and host-processing requirements<\/td>\nThe CPU provides flexible software-based JPEG compression<\/td>\nThe GPU provides parallel compression using available GPU compute resources<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n
Swipe horizontally to view all columns \u2192<\/div>\n

Benefits of Real-Time JPEG Compression<\/h2>\n

According to Ofer Pravda, VP Marketing & Sales at Gidel, real-time compression offers several system-level advantages. The system can store compressed image data during acquisition rather than first storing complete uncompressed images in large memory banks. In addition, compressing images in the FPGA before host transfer can reduce PCIe bandwidth, memory traffic, storage requirements, and host processing load.<\/p>\n

Gidel designed its FPGA JPEG encoder for streaming image processing with very low latency. Current Gidel specifications include performance beyond 1.8 GPixels\/s for 4:2:2 sampling and latency as low as 130 \u03bcs, depending on the implementation and configuration.<\/p>\n

Customizing the Processing Pipeline with ProcVision Suite<\/h2>\n

The ProcVision Suite<\/strong><\/a> provides a modular development environment for customizing Gidel FPGA imaging pipelines. Developers can combine Gidel\u2019s JPEG Compression IP with acquisition, buffering, ISP functions, and their own proprietary FPGA processing algorithms.<\/p>\n

Using ProcVision Suite, developers can adapt the FPGA acquisition and processing path to customer requirements. This lets developers position compression at the appropriate stage of the imaging pipeline and combine it with customer-specific processing before or after compression. Gidel can also provide part or full customization according to customer specifications.<\/p>\n

Supported Camera Interfaces and FPGA Platforms<\/h2>\n

ProcVision supports GigE Vision, CoaXPress, Camera Link, MIPI, and user-defined camera interfaces and protocols. The development environment supports Gidel FPGA platforms based on Altera FPGA<\/a> families.<\/p>\n

This allows engineers to integrate JPEG compression into different imaging architectures, from compact embedded systems and FantoVision Edge AI systems to PCIe frame grabbers, FPGA modules, and high-performance FPGA accelerator platforms.<\/p>\n

JPEG Compression Across Gidel FPGA Platforms<\/h3>\n

Gidel supports its JPEG Compression IP across several FPGA platforms, including:<\/strong><\/p>\n