To reduce risk, development time and time-to-deployment, the Gidel modules are supported by state-of-the-art development tools and a PCIe carrier board enabling to start developing immediately the application and FPGA code. A user may, for example, start developing an image processing IP using a streaming input from files and sending the IP output to a grabber for display, storage, analyzing, etc.
Gidel’s development suite includes a DRAM controller enabling: 1. Splitting the physical DRAMs into up to 16 separate logical memories, all operating in parallel. 2. Accessing simultaneously each logical memory by multiple sequential ports, each with its own clock and data width. For example, a 128 MB FIFO may be automatically generated by Gidel’s tools utilizing a 128 MB logical memory with a single write port and a single read port.