Gidel’s CertifEye Development Kit is an optimal solution for developing, validating, demonstrating and evaluating Image Processing (IP) and pipeline designs on FPGA.
The suite is designed to provide a complete and convenient envelop enabling the developer to focus strictly on the proprietary image processing design. The entire CertifEye flow is within a single FPGA, independent of the final target application(s). The CertifEye flow is composed of a pipeline that streams simulated data to the user image processing design under test (DUT) and then captures the design’s output stream for displaying, storing, analysis and/or co-processing on host software. The entire process is performed on a single FPGA without the need for additional peripheral connectivity or tools.
CertifEye suite is plug-and-play enabling the developer to begin at once the IP design development and validation. A simple design example provides the developer immediate hands-on familiarization with the system flow and supporting tools.
The final design can be ported to any Intel FPGA device or other vendors’ devices (FPGA or ASIC) by replacing basic libraries. To significantly reduce compilation time, initial design development may be on a small FPGA device and later compiled for the target device(s). The target implementation may use any FPGA board. For a full Imaging/Vision system solution, Gidel offers a number of off-the-shelf grabbers and FPGA accelerators that are designed to utilize these image processing blocks and Gidel Imaging Library (GIL).
CertifEye is supported by a powerful Gidel ecosystem that allows customizing the entire data flow, including the camera simulator(s), image processing and the grabbing path. The flow, for example, can be tailored to include multiple camera streams and a grabbing path based on one of Gidel’s FPGA Grabbers (ProcFG or InfiniVision) or the user’s own proprietary grabber. Gidel’s ecosystem includes: Development software, GUIs, API, Imaging IPs, templates, examples and variety of FPGA boards to meet cost-performance and interfacing requirements.