CertifEye Developer’s Kit

Gidel’s CertifEye Development Kit is an optimal solution for developing, validating, demonstrating and evaluating Image Processing (IP) and pipeline designs on FPGA.

 

The suite is designed to provide a complete and convenient envelop enabling the developer to focus strictly on the proprietary image processing design. The entire CertifEye flow is within a single FPGA, independent of the final target application(s). The CertifEye flow is composed of a pipeline that streams simulated data to the user image processing design under test (DUT) and then captures the design’s output stream for displaying, storing, analysis and/or co-processing on host software. The entire process is performed on a single FPGA without the need for additional peripheral connectivity or tools.
CertifEye suite is plug-and-play enabling the developer to begin at once the IP design development and validation. A simple design example provides the developer immediate hands-on familiarization with the system flow and supporting tools.

 

The final design can be ported to any Intel FPGA device or other vendors’ devices (FPGA or ASIC) by replacing basic libraries. To significantly reduce compilation time, initial design development may be on a small FPGA device and later compiled for the target device(s). The target implementation may use any FPGA board. For a full Imaging/Vision system solution, Gidel offers a number of off-the-shelf grabbers and FPGA accelerators that are designed to utilize these image processing blocks and Gidel Imaging Library (GIL).

 

CertifEye is supported by a powerful Gidel ecosystem that allows customizing the entire data flow, including the camera simulator(s), image processing and the grabbing path. The flow, for example, can be tailored to include multiple camera streams and a grabbing path based on one of Gidel’s FPGA Grabbers (ProcFG or InfiniVision) or the user’s own proprietary grabber. Gidel’s ecosystem includes: Development software, GUIs, API, Imaging IPs, templates, examples and variety of FPGA boards to meet cost-performance and interfacing requirements.

Contact Information

North America:

+1 408 969 0389

EMEA:

+972 4 610 2500

Asia Pacific:

+972 4 610 2500

Key Features

  • A complete flow for developing and validating user IP design, including:
    • Image streaming into user design
    • Grabbing from user design for storage, display and analysis
    • Host access via GUI, macros and user software
  • Ideal for design demonstration and evaluation by target end-user
  • Image source can be from the host computer’s HDD or user application
  • IP design portable to other FPGA devices and technologies
  • Flow implemented on single FPGA without the need for additional peripheral connectivity/tools
  • Simplicity:
    • Plug-and-play ready for immediate IP development
    • Insert IP design and test
    • Supported by simple design example for hands-on exploration from the start
  • Fixable data flow and ability to build other flows such as:
    • Two camera input and a single output
    • Output Vision system information
  • Enables developing/validating image processing pipeline with multi-IP blocks
  • Supported by Gidel’s eco-system:
    • CamSim: camera simulator
    • InfiniVision: multi-camera, multi-format grabber
    • ProcFG: grabber with image analyzing capabilities and GenICam
    • ProcWizard: enables fully tailoring user FPGA interfacing/grabbing flow
    • Grabbers: variety of grabbers with open FPGA for user image processing
    • GIL: Gidel Imaging Library (FPGA IPs)

CertifEye Components

FeatureSpecification
CertifEye TemplatesThe CertifEye templates enable customization such as defining the number of pixels or pixel components per clock and number of bits per pixel. Based on the templates, the flow can be used seamlessly on different Intel FPGA devices, starting from Stratix III and up to Stratix 10 and Arria 10 device families.
CamSimFor image processing development it is crucial to be able to stream large image or video data with the ability to resend the data. The CamSim camera simulator system enables streaming images or video to the user design under test. The images source may be from CamSim’s pattern generator or from image files on the hard drive. In addition, the CamSim API can be used to process image streams. For example, incoming images can be processed according to runtime calculated AGC parameters. Based on the CamSim, the system can be efficiently tested, debugged, demonstrated and evaluated. Image formats include: Raw, Mono, Bayer, RGB, RGBA, YUV, YCbCr.
ProcFG
Grabber system enabling to capture the image data stream, perform vision and image processing, and offload image data to the host computer. This grabber flow enables Regions Of Interest (ROIs) recognition by the FPGA processing and user run-time application to grab only relevant ROIs. The ability to grab ROIs reduces PCIe and memory bandwidth usage and enables balancing between the FPGA and host processing. The ProcFG supports GenICam standard and 3rd party image processing libraries via the GenTL.
InfiniVision Mult-Camera GrabberGrabber system enabling to capture multiple image streams of varying sensors, frame size and image formats. The InfiniVision may synchronize up to 100 cameras. InfiniVision has the capability to grab compressed heterogeneous image data. To further leverage this feature, Gidel offers on-FPGA real-time Lossless and JPEG compression.
ProcWizardA powerful developer’s application for simplifying the development task on FPGA and the integration with the software application. The ProcWizard enables multiple programs to access simultaneously the FPGA, full customization of the software driver, and programmable macros for automatic configuration and flow execution.
Download our data sheet for Proc 10S Acceleration System.