High-Performance Ultra Compact Acceleration Modules

Gidel offers a number of ultra-compact high-performance FPGA modules that can be mounted on a Gidel off-the-shelf PCIe carrier board or on a user or Gidel custom carrier board.  The modules provide a complete FPGA envelop ready for use while leaving flexibility for tailoring the peripheral system precisely to the system specifications via the carrier board. For custom carrier solutions, Gidel provides templates and a powerful development tools that enable to quickly develop the carrier board and to optimize the FPGA utilization for the system design. Gidel’s diverse module offerings include ultra-high-end modules based on Intel Stratix 10M FPGA and high-end ultra-compact solutions based on Intel Arria 10 FPGAs.


FPGAArria 10 160 GXArria 10 480 GXArria 10 270 GXArria 10 270 GXStratix 10
MX 2100
Logic Ele­ments160K480K270K660K2,073K
18x19 3122736166033747920
I/O PLL61281616
On-board DDR42/4 GB2/4 GB10 GB10 GB Up to 128 GB on Carrier board
Memory Throughput12 GB/s12 GB/s24 GB/s24 GB/s>400 GB/s
I/Os12x3.0V, 4x1.2V, 36x1.8V12x3.0V, 4x1.2V, 36x1.8V 42x3.0V, 4x1.2V, 52x1.8V42x3.0V, 4x1.2V, 52x1.8V374 I/Os:
26x3.3V, 96xLVDS, 72-bit DDR4
(2 Rx only)
(2 Rx only)
(2 Rx only)
(2 Rx only)
Transceivers speedUp to 14.2 Gb/sUp to 14.2 Gb/sUp to 14.2 Gb/sUp to 14.2 Gb/sUp to 26Gb/s
Dimensions49mm x 54mm49mm x 54mm58mm x
58mm x 62mm97.4mm x

Contact Information

North America:

+1 408 969 0389


+972 4 610 2500

Asia Pacific:

+972 4 610 2500

Gidel’s Powerful Development Suite

To reduce risk, development time and time-to-deployment, the Gidel modules are supported by state-of-the-art development tools and a PCIe carrier board enabling to start developing immediately the application and FPGA code. A user may, for example, start developing an image processing IP using a streaming input from files and sending the IP output to a grabber for display, storage, analyzing, etc.

Gidel’s development suite includes a DRAM controller enabling: 1. Splitting the physical DRAMs into up to 16 separate logical memories, all operating in parallel. 2. Accessing simultaneously each logical memory by multiple sequential ports, each with its own clock and data width. For example, a 128 MB FIFO may be automatically generated by Gidel’s tools utilizing a 128 MB logical memory with a single write port and a single read port.

Proc Dev Kit and ProcVision Suite

  • Enables immediate mapping of board resources to the application needs including tailored host interface and dividing the DRAM into application logical memory units by automatically generating an ASP (Application Support Package) optimized to the system requirements.
  • Enables tailoring high-end grabber(s) and Imaging/Vision acceleration flow in an intuitive and simple manner by customizing the ASP, software and the FPGA design code.
  • Enables parallel access of multiple applications on the module FPGA thus expediting the development and improving system reliability. For example, firewall and compression may be accelerated simultaneously on the same FPGA and controlled by independent applications

With over 25 years of proven experience, our technology has been implemented in diverse markets spanning from Compute accelerators to AI and high-end Vision solutions.

Download our data sheets for the Gidel Modules Computation Accelerators.