FPGA Acceleration in a Reconfigurable Supercomputer
A reconfigurable supercomputer can address demanding HPC workloads by combining programmable FPGA processing with scalable high-speed connectivity. At the same time, data centers face exponential data growth and increasing power demands, while traditional CPU-based architectures can require substantial increases in power and cooling as workloads scale. Gidel’s FPGA acceleration technology provides an alternative architecture based on massive parallelism and direct high-speed FPGA connectivity.
In addition, Gidel’s direct FPGA connectivity allowed FPGA nodes to communicate without routing inter-FPGA data through the host CPU. This architecture supported advanced topologies such as 3D and 12D Torus, and 6D or 24D Hypercube configurations. As a result, the architecture enabled scalable communication for HPC workloads that require high throughput and low latency.
CHREC Builds a Reconfigurable Supercomputer Using Gidel FPGA Boards
The Center for High-Performance Reconfigurable Computing (CHREC), funded by the National Science Foundation, set out to create the fastest research-focused reconfigurable supercomputer in the world. Their goal was to evaluate architectures that deliver both high performance and low energy consumption.
Initially, CHREC researchers explored CPU-socket accelerators but encountered instability, high costs, and under-performing I/O bandwidth. They shifted toward PCIe FPGA boards and evaluated multiple vendors. After extensive testing, CHREC selected Gidel for its performance, stability, and superior technical support.
| Architecture | Novo-G Configuration |
|---|---|
| Computing Approach | FPGA-based reconfigurable computing |
| Research Organization | Center for High Performance Reconfigurable Computing (CHREC) |
| Gidel FPGA Platforms | PROCStar-III, PROCStar-IV, and ProceV D8 |
| FPGA Interconnect | Direct FPGA-to-FPGA links |
| Network Architecture | Scalable multi-dimensional topology, including 3D torus configurations |
| Host Involvement | Inter-FPGA communication can occur without routing data through the host CPU |
| Primary Use | HPC acceleration, reconfigurable-computing research, and large-scale FPGA application development |
| Key Architectural Benefit | Scalable low-latency communication between FPGA nodes |
Why Gidel Was Chosen for the Novo-G Supercomputer
- Highest FPGA speed grades available at the time
- Leading FPGA-to-host and FPGA-to-FPGA throughput at the time
- Large on-board memory with low latency
- Mature API and run-time environment for rapid development
The resulting system, called Novo-G, used hundreds of Gidel FPGA cards (ProcStar III/IV and ProceV D8). CHREC interconnected these cards using Gidel’s direct FPGA links, creating a high-speed 3D torus network that enabled direct FPGA-to-FPGA computation without routing the data through the host CPU.
Reconfigurable Supercomputer Performance with FPGA Acceleration
Novo-G demonstrated substantial performance and energy-efficiency advantages for selected reconfigurable-computing workloads. It won the 2012 Alexander Schwarzkopf Prize for technology innovation and, on the 3D FFT kernel, demonstrated nearly 2× the performance of Anton and approximately 50× the performance of BlueGene/L.
This success validated Gidel’s approach to high-throughput, low-latency FPGA acceleration for large-scale HPC infrastructure.
Supported FPGA Platforms
Gidel’s FPGA acceleration solutions span multiple hardware platforms for HPC, data processing, and reconfigurable computing. These include PCIe FPGA accelerator boards, FPGA modules, and high-performance FPGA platforms designed for applications that require large data throughput, low latency, and scalable parallel processing.
Depending on the system architecture, engineers can use Gidel FPGA platforms for host-connected acceleration, direct FPGA-to-FPGA communication, custom data processing, and multi-board computing architectures.
FPGA Development with ProcDev Kit
Gidel’s ProcDev Kit provides the development environment required to build and integrate custom FPGA processing on Gidel platforms. It supports FPGA application development, hardware integration, data movement, and communication between the host and FPGA resources.
For reconfigurable computing and HPC applications, ProcDev Kit allows engineers to develop custom FPGA logic while using Gidel’s hardware infrastructure, APIs, and communication capabilities. This helps reduce integration effort when moving from algorithm development to multi-board or system-level deployment.
Long-Term Collaboration and Scalable Architecture
Gidel and the CHREC team have collaborated for more than a decade. Moreover, the architecture supported continued system expansion. A Gidel FPGA board could manage a large multi-dimensional communication network, while engineers could add additional nodes to scale the cluster.
Further Resources on FPGA Acceleration and Reconfigurable Computing
Learn more about Gidel’s FPGA Acceleration cards: FPGA Compute Accelerators.
Read more about reconfigurable computing research at CHREC: Novo-G Research Paper.
