Proc10A: High-Performance FPGA Accelerator Card
The Proc10A™ is a flexible, high-performance, low-power FPGA accelerator card built on Altera’s Arria® 10 FPGA. Designed for networking, and demanding data-processing workloads, it not only delivers robust computing power but also ensures excellent energy efficiency, making it ideal for modern systems.
FPGA Accelerator Card Architecture and Memory Capabilities
With up to fifteen 14.2 Gb/s full-duplex transceivers and extensive memory options, the Proc10A FPGA accelerator card delivers outstanding I/O throughput and on-board processing performance. Additionally, its multi-level memory architecture includes:
-
Up to 32 GB DDR3 ECC SODIMM for high-capacity requirements.
-
On-board 1 GB DDR3 SDRAM for low-latency local operations.
-
Dedicated FPGA memory blocks (M20K and MLABs) for real-time data handling.
As a result, the Proc10A is particularly effective for low-latency, high-bandwidth storage, networking, and advanced imaging applications. In addition, its architecture enables engineers to meet demanding performance goals without sacrificing efficiency.
High-Speed Connectivity in a Compute Accelerator
The Proc10A integrates an 8-lane PCI Express Gen3 bridge, enabling fast and efficient co-processing between the host CPU and the FPGA. Furthermore, for applications requiring tightly coupled FPGA-CPU functionality, the Proc10A SoC family includes an embedded ARM processor based on Arria® 10 SoC FPGAs, providing developers with even greater design flexibility. Consequently, the Proc10A supports a wide range of high-performance, mission-critical applications.
Development Tools for High-Performance FPGA Platforms
Supported by Gidel’s advanced development suite, the Proc10A FPGA accelerator card simplifies integration and accelerates deployment. Moreover, it supports C and HDL-based workflows, reducing engineering time, improving system reliability, and shortening time-to-market. Therefore, teams can bring powerful FPGA-based solutions to market faster and with greater confidence.
Why Choose the Proc10A FPGA Accelerator Card?
-
Built on Altera Arria® 10 FPGA for reliable, proven performance.
-
Up to 15 full-duplex 14.2 Gb/s transceivers for high-speed data processing.
-
Multi-level memory architecture with up to 32 GB DDR3 ECC SODIMM.
-
PCIe Gen3 x8 connectivity for seamless FPGA-CPU interaction.
-
SoC variant with ARM processor for tightly coupled processing.
-
Backed by Gidel’s development tools, ensuring faster and more efficient delivery.
For more accelerator card options, visit FPGA Compute Acceleration – Gidel
Target applications
General
- 1.6 MB embedded MLAB (640-bit) SRAM blocks
- 6.75 MB embedded M20K (20K-bit) SRAM blocks
- Up to 32 GB DDR3 SDRAM (2x 16GB SoDIMMs)
- On-board 1 GB DDR3 SDRAM
- 270K, 660K, and 1150K logic elements
- Up to 3,036 18x19 embedded 18x19 multipliers
- Embedded M20K and MLAB blocks
- Up to 15x 14.1 Gb/s transceivers
- 1.6 Gb/s LVDS performance
- Up to 2,713 M20K blocks @ 450 MT/s for total of ~5 TB/s
- DDR3 SDRAM for total at 4.5 GB/s
- Flexible clocking system
- Temperature monitoring
Connectivity
- 3x SFP+
- 1 x QSFP+
- 2x PHS (Gidel High Speed Connector)
Environmental conditions
- Continuous Operation: 10 - 80% (non-condensing)
- Peak Operation: 10 - 90% (non-condensing)
Development tools
Generation of environment FPGA code, including all board/IP constrains and user logic wrapper
Generation of dedicated application driver supported by API
Splitting of physical on-board memories into logical memories with independent parallel access to/from user logic
The Proc10A FPGA accelerators is highly flexible and available with various FPGA and connector options.
For additional Proc10A models, including SoC, and other FPGA speed grades, contact Gidel.
Proc10A Accelerator Card: FPGA resources comparison
| Base model | Proc10A-027 Series | Proc10A-066 Series | Proc10A-115 Series |
|---|---|---|---|
| FPGA | Altera Arria 10 GX 270 | Altera Arria 10 GX 660 | Altera Arria 10 GX 1150 |
| FPGA-ALM | 101,620 | 250,540 | 427,200 |
| FPGA-M20K | 750 | 2,133 | 2,713 |
| FPGA - 18 x 19 Multiplier | 1,660 | 3,556 | 3,036 |
| Peripheral Memory: | |||
| 1 GB | 1 GB | 1 GB | |
| 5.6 GB/s | 5.6 GB/s | 5.6 GB/s | |
| 0, 8,16 GB | 0, 8,16 GB | 0, 8,16 GB | |
| 8.96 GB/s | 8.96 GB/s | 8.96 GB/s | |
| 0, 8,16 GB | 0, 8,16 GB | 0, 8,16 GB | |
| 8.96 GB/s | 8.96 GB/s | 8.96 GB/s |
Development Tools
For HDL Design Flow
- Generation of environment FPGA code, including all board/IP constrains and user logic wrapper
- Generation of dedicated application driver with API support
- Splitting of physical on-board memories into logical memories with independent parallel access to/from user logic
- Altera Tools: Quartus Prime Pro, including QSys and DSP builder
Leonardo Solis-Vasquez and Andreas Koch.
Technische Universität Darmstadt, Embedded Systems and Applications (ESA) Group, Darmstadt, Germany
Open
