Gidel Launches New Real-Time FPGA Lossless Encoder

FPGA Lossless Encoder for Real-Time Data Processing

Gidel’s FPGA Lossless Encoder delivers real-time 1 GB/s encoding while using a very small FPGA footprint and consuming under 0.2 W. The mathematically reversible compression preserves the original data for exact reconstruction while reducing storage requirements by more than 50%.

Why FPGA-Based Reversible Compression Matters Today

High-bandwidth imaging, HPC, and sensor systems increasingly generate more data than storage, memory, and host interfaces can handle efficiently. Reversible compression helps reduce this data volume without losing information, making it valuable when every original bit must remain recoverable.

Implementing compression in the FPGA allows the system to reduce data earlier in the processing path, before it reaches host memory or storage. This can lower downstream bandwidth requirements, reduce storage demand, and preserve CPU resources for other processing tasks.

Real-Time Lossless Compression in FPGA Hardware

Gidel’s reversible compression core runs directly in FPGA hardware as part of the real-time data path. Because the compression engine uses dedicated FPGA logic, it can process incoming data continuously without relying on host software or CPU scheduling.

In the referenced implementation, the core achieved real-time encoding at 1 GB/s while using only a very small portion of the FPGA. The compression is mathematically reversible, so the system can reconstruct the original data exactly with zero degradation.

Gidel’s imaging platforms can combine the FPGA Lossless Encoder with acquisition from GigE Vision cameras, CoaXPress cameras, Camera Link cameras, and user-defined protocols.

Ultra-Efficient FPGA Lossless Encoder Design

The Gidel FPGA reversible compression core uses only a small amount of FPGA logic and consumes less than 0.2 W. In the referenced HawkEye Arria 10-480 implementation, the complete IP occupies approximately 1% of the FPGA resources. This compact footprint makes the core well suited for integration into Gidel FPGA platforms where logic, power, and bandwidth efficiency are critical.

Real-time reversible compression can also improve system efficiency beyond storage reduction. By compressing data before host transfer or recording, the system can reduce memory traffic, PCIe bandwidth, and SSD storage requirements. As a result, engineers can preserve more system bandwidth for acquisition, processing, and other real-time functions.

Supported FPGA Platforms

Gidel’s FPGA Lossless Encoder can be integrated across Gidel FPGA platforms, including PCIe frame grabbers, Mini FPGA Modules, FantoVision Edge AI systems, and FPGA compute accelerators. These platforms use Altera FPGA technology and provide the FPGA resources, memory architecture, and high-bandwidth interfaces required for real-time acquisition, processing, and compression.

Depending on the platform and system architecture, engineers can place the lossless encoder directly in the FPGA data path alongside acquisition, buffering, preprocessing, and other real-time functions. This allows compressed data to reach host memory or storage earlier in the pipeline, reducing downstream bandwidth and storage requirements.

Gidel supports its FPGA Lossless Encoder across several FPGA platforms, including:

• PCIe Frame Grabbers
• FantoVision Edge AI Systems
• Mini FPGA Modules
• FPGA Compute Accelerators

Customizing the Processing Pipeline with ProcVision Suite

The ProcVision Suite provides a modular development environment for integrating the FPGA Lossless Encoder into customer-specific imaging and data-processing pipelines. Developers can combine compression with acquisition, buffering, preprocessing, and proprietary FPGA algorithms.

ProcVision supports GigE Vision, CoaXPress, Camera Link, MIPI, and user-defined camera interfaces and protocols. Using ProcVision, developers can adapt the acquisition and processing path to application requirements and position lossless compression at the appropriate stage of the FPGA pipeline.

Improving Storage Efficiency and Sensor-System Performance

Real-time reversible compression is especially valuable for systems that capture large volumes of sensor data in the field. Applications with limited storage capacity or restricted uplink bandwidth can benefit directly. Reducing data size by more than 50% can significantly increase effective recording capacity and reduce storage or downstream bandwidth requirements. Depending on the system architecture, it can also support higher aggregate sensor throughput.

Initial evaluations used hundreds of images supplied by Gidel’s strategic partners. The IP is available for customer deployments.

Compression and Encryption Roadmap

At the time of the announcement, Gidel was also developing FPGA-based encryption IPs to complement its compression technologies. The intended architecture combined reversible compression followed by encryption, enabling efficient data-reduction and security pipelines for cloud, edge, and imaging applications.

The broader FPGA processing architecture was intended to combine compression, encryption, acquisition, and image-processing functions within modular data pipelines. Such architectures were aimed at recording systems, mapping, autonomous platforms, security applications, and other high-bandwidth workloads.

Reversible Compression Demonstration at ISC 2018

Gidel demonstrated the reversible compression IP at ISC 2018 in Frankfurt, Germany (booth G-814), where visitors could see the technology operating in real time.

Learn more about Gidel’s FPGA Lossless Image Compression.