Accelerator Board

High Performance Scalable Compute Accelerators

  • Stratix 10 GX/SX FPGA
  • Up to 2,800K logic elements
  • For SX devices, Quad-core 64-bit ARM Cortex-A53 MPCore processor, contact Gidel.
  • PCIe x16 Gen. 3 or stand-alone
  • Up to 16× 25 Gb/s reconfigurable transceivers (total of 400 Gb/s)
  • Supported by the Proc Dev Kit FPGA Programming SDK
  • Form factor: full-height, double-slot, ¾ length PCI Express card

Proc10S: Accelerator Board

The Proc10S™ is a high-performance, scalable accelerator board built on Altera Stratix® 10 GX FPGA technology. Designed for compute-intensive, high-bandwidth, and low-latency workloads, it not only delivers peak single-precision performance of up to 10 TFLOPS but also ensures the flexibility needed for next-generation Data Centers applications. With 2.8 million logic elements, 260 GB DDR4 memory, and an optional Quad-core 64-bit ARM Cortex-A53 processor, the Proc10S provides the processing power and adaptability required for evolving infrastructures.


Performance and Memory

This powerful accelerator integrates a 16-lane PCIe Gen3 interface with 25/14.1 Gb/s SERDES transceivers for ultra-fast connectivity. Additionally, it supports up to 400 Gb/s throughput via 4 × QSFP28 or a combination of 2 × QSFP28, 2 × SFP28, and Gidel’s proprietary high-speed PHS connector. As a result, the Proc10S delivers unmatched bandwidth and responsiveness for HPC, storage, networking, and real-time data-processing environments.


Connectivity and Expansion Options

The Proc10S offers abundant I/O and expansion capabilities, ensuring seamless integration into diverse Data Centers infrastructures. Furthermore, its flexible architecture supports a wide range of applications, including broadcasting, video analytics, 5G infrastructure, and security tasks such as deep packet inspection and fraud detection. Consequently, it provides the scalability and versatility required to address the most demanding workloads.


Development Tools

Supported by Gidel’s advanced development suite, the Proc10S accelerator board streamlines integration and simplifies development. Moreover, it supports C and HDL-based workflows, reducing engineering effort, enhancing reliability, and shortening time-to-market for mission-critical solutions. In addition, its robust toolchain allows developers to maximize FPGA resources efficiently, ensuring long-term value in high-performance environments.


Why Choose the Proc10S Accelerator Board?

  • Altera Stratix® 10 FPGA with up to 2.8 million logic elements.

  • 260 GB DDR4 memory with optional ARM Cortex-A53 SoC.

  • Up to 10 TFLOPS single-precision performance.

  • 400 Gb/s total I/O bandwidth with PCIe Gen3 × 16 and QSFP28 ports.

  • Ideal for Data Centers, HPC, 5G, security, and AI workloads.

For more accelerator board options, refer to FPGA Compute Acceleration – Gidel

            Target applications:

  • DSP (Digital Signal Processing)
  • HPRC (High Performance Reconfigurable Computing)
  • High-speed, Low-latency Networking
  • Network Analysis
  • Life Science Applications
  • Linear Algebra and 3D Applications
  • Computational Finance and HFT
  • Data Analytics
  • Data Centers
  • Deep Packet Inspection
  • Surveillance
  • Machine Vision
  • Imaging
  • High Performance Acquisition Systems

General

FPGA
Altera Stratix 10 GX
Memory
  • Embedded MLAB (640-bit) SRAM blocks
  • 11,721 M20K (20K-bit) SRAM blocks
  • Up to 256 GB DDR4 SDRAM SoDIMM with throughput of up to 13.5 GB/s
  • 4 GB on-board DDR4 SDRAM with throughput of up to 48 GB/s
Processing Resources
  • Up to 2,800K logic elements
  • H-TILE supporting up to 16x 25 Gb/s SERDES I/O
  • For SX devices, Quad-core 64 bit ARM Cortex-A53 MPCore processor
  • Peak fixed-point performance 23.0 TMACS
  • Peak floating-point performance 9.2 TFLOPS
  • M20K blocks at up to 58 TB/s sustain access
  • Up to 11,520 18x19 variable precision multipliers
  • Up to 10x 25 Gb/s reconfigurable transceivers
  • Quad-core 64-bit ARM Cortex-A53 MPCore @ max processor speed of 1.5 GHz
Board Management
  • Flexible clocking system
  • Temperature monitoring
  • Internal voltage monitoring
  • Support for Partial Reconfiguration and CvP
Form Factor
Dual-slot, full-height ¾ length PCIe card
Power
Typically, less than 100W: Depends on user application and FPGA Type
Cooling
Passive cooling | Active cooling (fan)
MTBF
>Million hours (With Passive Cooling)

Connectivity

Host Interface
PCIe x16 Gen.3
I/O
  • 4x QSFP28
  • 2x SFP28
  • Gidel proprietary high-speed (PHS) connector

Environmental conditions

Temperature
Operating ambient air temperature: 0 – 55° C
Humidity
  • Continuous Operation: 10 - 80% (non-condensing)
  • Peak Operation: 10 - 90% (non-condensing)
Environmental Compliance

Development tools

Gidel ProcDev Kit
for HDL design flow:
  • Generation of FPGA environment code, including all board/IP constraints and a user-logic wrapper
  • Generation of a dedicated application driver with an API
  • Splitting physical on-board memories into logical memories, each with independent, parallel access to/from user logic
Altera Tools
Quartus Prime Pro, including QSys and DSP builder
P10S085S0-C
Stratix 10 GX 850-2, 2GB DDR4, PHS only,
P10S085S3-C
Stratix 10 GX 850-2, 2GB DDR4, PHS + 2xQSFP + 2xSFP+, links up top 16Gb/s
P10S085S4-B
Stratix 10 GX 850-2, 2GB DDR4, 4xQSFP, links up top 26Gb/s
P10S280S0-C
Stratix 10 GX 2800-2, 4GB, PHS only,
P10S280S3-C
Stratix 10 GX 2800-2, 4GB DDR4, PHS + 2xQSFP + 2xSFP+, links up top 16Gb/s
P10S280S4-B
Stratix 10 GX 2800-2, 4GB DDR4, 4xQSFP, links up top 26Gb/s

Please contact us if you need a customized solution!

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Development Tools

Proc Dev Kit
For HDL Design Flow
  • Generation of environment FPGA code, including all board/IP constrains and user logic wrapper
  • Generation of dedicated application driver with API support
  • Splitting of physical on-board memories into logical memories with independent parallel access to/from user logic
  • Altera Tools: Quartus Prime Pro, including QSys and DSP builder
Documentation
Proc10S Datasheet Open
Proc10S Block Diagram Open


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