Gidel Introduces New FPGA JPEG Compression IP

JPEG FPGA Compression IP for Real-Time Imaging

Gidel’s FPGA JPEG compression IP delivers real-time encoding with very low latency, compact FPGA resource usage, and 4× higher throughput utilization than comparable solutions. Designed for high-speed Imaging & Vision systems, it processes image data directly in the FPGA path, reducing the amount of data that must be transferred, stored, or handled downstream.

High-Speed FPGA Image Compression

Gidel, a long-time leader in FPGA-based Vision and Imaging solutions, has introduced a new real-time JPEG encoder for high-speed and embedded imaging systems. The architecture combines compact FPGA resource usage with high processing performance and supports very wide images, making it suitable for demanding high-resolution pipelines.

The encoder processes image data directly on the FPGA and supports selectable quality settings, allowing customers to balance image quality, bandwidth, and storage requirements. It accepts YCbCr input, with optional conversion from RGB, Bayer, or monochrome formats.

Designed for High-Bandwidth Imaging Applications

The Gidel JPEG Encoder on FPGA targets applications that require real-time compression at high pixel rates. Typical applications include large-format cameras, multi-camera systems, recording systems, broadcasting, surveillance, smart cities, embedded vision, and other high-bandwidth imaging systems.

For high-bandwidth camera systems, engineers can implement JPEG compression in the FPGA close to the image source. When engineers integrate the FPGA into a camera or embedded imaging platform, compression can reduce the amount of image data transferred downstream. When an FPGA frame grabber performs JPEG compression after camera acquisition, it can reduce PCIe bandwidth, memory traffic, storage requirements, and host CPU/GPU load while maintaining a real-time FPGA processing pipeline.

Gidel’s imaging platforms can combine JPEG compression with acquisition from GigE Vision cameras, CoaXPress cameras, Camera Link cameras, and user-defined protocols.

FPGA Compression vs CPU and GPU Compression

The location of the JPEG encoder in the imaging architecture affects when image data is compressed and how much uncompressed data must move through the rest of the system. FPGA compression can operate directly in the acquisition and image-processing path before the system transfers the data to host memory.

Benefits of Real-Time JPEG Compression

According to Ofer Pravda, VP Marketing & Sales at Gidel, real-time compression offers several system-level advantages. The system can store compressed image data during acquisition rather than first storing complete uncompressed images in large memory banks. In addition, compressing images in the FPGA before host transfer can reduce PCIe bandwidth, memory traffic, storage requirements, and host processing load.

Gidel designed its FPGA JPEG encoder for streaming image processing with very low latency. Current Gidel specifications include performance beyond 1.8 GPixels/s for 4:2:2 sampling and latency as low as 130 μs, depending on the implementation and configuration.

Customizing the Processing Pipeline with ProcVision Suite

The ProcVision Suite provides a modular development environment for customizing Gidel FPGA imaging pipelines. Developers can combine Gidel’s JPEG Compression IP with acquisition, buffering, ISP functions, and their own proprietary FPGA processing algorithms.

Using ProcVision Suite, developers can adapt the FPGA acquisition and processing path to customer requirements. This lets developers position compression at the appropriate stage of the imaging pipeline and combine it with customer-specific processing before or after compression. Gidel can also provide part or full customization according to customer specifications.

Supported Camera Interfaces and FPGA Platforms

ProcVision supports GigE Vision, CoaXPress, Camera Link, MIPI, and user-defined camera interfaces and protocols. The development environment supports Gidel FPGA platforms based on Altera FPGA families.

This allows engineers to integrate JPEG compression into different imaging architectures, from compact embedded systems and FantoVision Edge AI systems to PCIe frame grabbers, FPGA modules, and high-performance FPGA accelerator platforms.

JPEG Compression Across Gidel FPGA Platforms

Gidel supports its JPEG Compression IP across several FPGA platforms, including:

• PCIe Frame Grabbers
• FantoVision Edge AI Systems
• Mini FPGA Modules
• FPGA Compute Accelerators

Depending on the platform and system architecture, engineers can perform JPEG compression alongside acquisition and image processing before transferring the image stream to the host.

Gidel’s Image-Processing IP Library

The JPEG Compression IP is part of Gidel’s broader FPGA image-processing environment, which combines acquisition, compression, image enhancement, buffering, and customer-specific processing within FPGA-based Imaging & Vision systems.

Together with Gidel’s FPGA hardware, development tools, and imaging infrastructure, engineers can integrate the JPEG encoder into complete real-time imaging pipelines for acquisition, processing, recording, and data transfer.

See the JPEG Compression IP in Action

Gidel demonstrated the FPGA JPEG Compression IP at the VISION show in Stuttgart, Germany, where visitors could view real-time compression demonstrations and evaluate the performance of Gidel’s compression technology.

Learn more about Gidel’s FPGA JPEG Compression IP