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FPGA Image Compression IPs

Gidel FPGA-based image compression IPs deliver real-time compression for demanding Imaging & Vision applications. Designed for ultra-high throughput, low latency, and efficient FPGA resource utilization, they reduce bandwidth, storage requirements, and system bottlenecks across industrial, medical, defense, and scientific imaging systems.

Gidel Real-Time FPGA Image Compression IPs

Real-Time FPGA Image Compression IPs: Overview & Comparison

Features
Encoder Name JPEG LL Q+
Compression Method Standard JPEG compression Bit-perfect lossless compression Proprietary compression that
maintains original SNR
Main Benefit Selectable compression
quality with broad compatibility
Fully reconstructs the
original image data
Maintains original SNR while
improving compression ratios
Supported
Image Formats
  • YCbCr
  • RGB
  • Bayer
  • Monochrome
  • CFA, including Bayer
  • RGB
  • Monochrome
  • CFA, including Bayer
  • RGB
  • Monochrome
Compression Ratio Selectable according to
image-quality requirements
1:2.3 in real-world video
tests at 8 bits/pixel
Up to 10:1+
Throughput Beyond 1.8 GPixels/s
for 4:2:2 sampling
Beyond 1 Gpixel/s Beyond 1.2 GPixels/s
Latency As low as 130 μs Real-time compression Less than one frame period
Compression Modes Individual JPEG images Frame and video compression
using I and P frames
Single-frame and continuous
video compression
Camera
Setup
Optimized for moving cameras Moving and static cameras Optimized for static cameras
Supported
Bit Depth
  • 8 bits
  • Other – upon request
  • 8 bits
  • Other – upon request
  • 8 bits
  • Other – upon request
Supported Platforms Available on All Gidel FPGA Platforms

Low-Latency FPGA Compression with Modular Image Processing

Gidel FPGA platforms can combine real-time compression with image enhancement and processing directly within the acquisition flow. Optional FPGA processing includes HDR, detection, and other image enhancements. Customers can also integrate custom algorithms alongside Gidel IPs. This modular approach reduces host CPU and GPU load while maintaining low-latency performance for Imaging & Vision systems.

Need more information?




    Block Diagram: Example for Compression in the FPGA data flow

    Compressing Image Data - Not Image Quality

    As today’s cameras deliver higher resolutions and frame rates and new systems architectures such as vision on the edge have bandwidth limitations, compression becomes a key challenge for advanced image processing applications. But how can the data throughput be reduced without jeopardizing the image and inspection quality?

    Read article

    Additional FPGA-Based Imaging Solutions

    Explore additional Gidel FPGA-based solutions for demanding processing, acceleration, and system-integration applications.

    Need Help Choosing?

    Our experts can help you find the right product for your specific requirements.

    • Free product consultation
    • Technical specifications review
    • Custom configuration options
    • Volume pricing available

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