The HawkEye is a low-profile PCIe accelerator based on Intel’s Arria 10 FPGAs . The platform boasts up to 18 GB DDR4 on-board memory, 2 SFP+ links for a maximum of 28 Gb/s, and a PCIe x8 Gen. 3 host interface. The Arria 10 FPGA provides up to 480K LEs and IEEE floating-point capability. The HawkEye’s memory scheme is composed of embedded SRAM memory, 1-2 GB DDR4, and up to 16 GB of DDR4 SoDIMM (only for boards with 480 devices). The DDR memory may be accessed via up to 48 parallel ports simultaneously.
The HawkEye family includes an option for SoC Hard Processor System (HPS) based on Arria 10 SX devices with an embedded dual core ARM processor. The SoC boards are supported by a MicroSD memory card allowing storage of large program images for stand-alone mode.
The HawkEye accelerator board exhibits an impressive power efficiency, starting at less than 12W. The board is fortified by abundant I/O interface possibilities, including RS422, Opto-coupler, external clock, LVDS, LVTTL (3V), and 30V/0.9A output. The HawkEye can operate as a PCIe-based platform or as a stand-alone compute accelerator. The system has been designed for exceptional high reliability with an MTBF beyond 1 million hours.
The HawkEye is supported by Gidel’s unique proprietary tools for developing on FPGA. These tools offer a solution that is unique in the market and can be used together with Intel’s design tools to achieve unmatched development efficiency and efficacy. The Gidel development tools suite includes Gidel’s Developer’s kit as well as Gidel HLS (i++) ASP based on Intel’s SDK.
Contact Information
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+1 408 969 0389
EMEA:
+972 4 610 2500
Asia Pacific:
+972 4 610 2500
- lntel Arria 10 GX FPGA, 160 or 480
- Option for SoC :
- Arria 10 SX FPGA, 160 or 480
- Hard Processor System (HPS) with an embedded dual core ARM processor
- PCIe x8 Gen. 3 Express or stand-alone
- Form factor: low profile
- Low power, starting at less than 12W
- 2x SFP+ cages
- MTBF > million hours
- Cost-effective, starting at < $1,000
- Dedicated features that enable tailoring to vertical markets
- Up to 1.2 GFLOPS processing capability
- Multi-level memory structure (18+ GB); sustained throughput of ~16 GB/s for on-board memory as follows:
- Enhanced MLAB (640-bit) SRAM blocks
- Up to 28,620 M20K (20K-bit) SRAM blocks (572 Mb) at a throughput of up to 128 TB/s at 450 MHz
- 2 GB DDR4 on-board memory at a maximum sustained throughput of 5.4 GB/s
- 8-16 GB DDR4 ECC SoDIMM Bank for maximum sustained throughput of 10.8 GB/s (480 device only)
- On board user flash (optional)
- Typical system freqeuency: 150-450 MHz
- Flexible clocking system
- Supported by Gidel’s Developer’s Kit
- Simultaneous acceleration of multiple applications or processes
- Unmatched HDL design productivity
- Simple integration with software applications
- Supported by Gidel’s HLS (I++) ASP based on Intel’s SDK (for Arria 10 480 only)
- Network Security, Processing and Analysis
- DSP and High Performance Reconfigurable Computing (HPRC)
- Computational Finance and High Frequency Trading (HFT)
- Deep Packet Inspection
- Life Science Applications
- Data Analytics
- Surveillance, Machine Vision, and Imaging
| Feature | Specification |
|---|---|
| FPGA | • Intel Arria 10 GX/SX • 160K or 480K logic elements • Embedded 18x19 multipliers • Embedded M20K and MLAB blocks • Up to 2x 12.5/14.1 Gb/s transceivers • 1.6 Gb/s LVDS performance • SoC Hard Processor System (HPS) with an embedded dual core ARM processor |
| Memory | • Embedded MLAB (640-bit) SRAM blocks • M20K (20K-bit) SRAM blocks • Up to 16 GB DDR4 SDRAM (SoDIMM) • Up to 2 GB on-board DDR4 SDRAM |
| Processing Performance | • Up to 1,431 M20K blocks @ 450 MT/s for a total of ~128 TB/s • Up to 2 GB DDR4 SDRAM for a total of 5.6 GB/s • Up to 16 GB DDR4 SDRAM for a total of 10.8 GB/s • Up to 2,736 18x19 multipliers |
| MTBF | > million hours |
| Form Factor | PCIe low-profile |
| Host Interface | PCIe x8 Gen.3 |
| I/O | 2x SFP+ |
| GPIO | • RS422 • Opto-coupler • LVDS and LVTTL (3V) • 30V/0.9A output driver • External clock |
| Development Tools | • Gidel ProcDev Kit for HDL design flow: o Generation of dedicated application driver o Splitting of physical on-board memories into logical memories with independent parallel access to/from user logic o Generation of environment FPGA code, including all board/IP constrains and user logic wrapper • Intel Tools: Quartus Prime Pro, including QSys and DSP builder • Gidel HLS (i++) ASP for use with Intel’s HLS compiler |
| Acceleration Board | FPGA Devices | Speed Grade | On-Board DDR4 Memory | I/O interface |
|---|---|---|---|---|
| HawkEye-16 | Arria 10 160 GX | 2 | 1GB | None |
| HawkEye-20G-16 | Arria 10 160 GX | 2 | 1GB | 2x SFP+ |
| HawkEye-48 | Arria 10 480 GX | 3 | 1GB+0-16GB SoDIMM | None |
| HawkEye-20G-48 | Arria 10 480 GX | 3 | 1GB+0-16GB SoDIMM | 2x SFP+ |
*For availability of additional HawkEye models, including SoC, 2 GB on-board, and other FPGA speed grades, please contact Gidel Sales.
Download our data sheet for the HawkEye 20 Gbps Arria 10 FPGA Computation Accelerators.