Gidel’s latest high-performance scalable compute acceleration system, the Proc10S, pushes data processing power to new heights with peak single precision performance of up to 10 TFLOPS. The Proc10S features an Intel Stratix 10 FPGA with up to 2.8 million logic elements, 260 GB DDR4 memory, and an option for a SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor.
The Proc10S boasts a 16-lane PCIe Gen. 3 host interface and 25/14.1 Gb/s SERDES I/O transceivers for ultra-fast connectivity to the FPGA. Abundant transceiver I/O connectivity enables a total of 400 Gb/s via 4xQSFP28 or a combination of 2xQSFP28, 2x SFP28 and RGMII/Gidel proprietary high-speed connector (PHS).
The Proc10S offers designers huge logic resources with incredible flexibility and performance capabilities to meet the most demanding design requirements. The Proc10S can address the design challenges of virtually all end markets, including HPC, storage, broadcast, medical, and test and measurement.
The Proc10S is supported by Gidel’s unique proprietary tools for developing on FPGA. These tools offer a solution that is unique in the market and can be used together with Intel’s design tools to achieve unmatched development efficiency and efficacy. The Gidel development tools suite simplifies significantly the hardware-software integration and offers powerful IPs for on-FPGA real-time data management and data compression.
Contact Information
North America:
+1 408 969 0389
EMEA:
+972 4 610 2500
Asia Pacific:
+972 4 610 2500
- Stratix 10 GX/SX FPGA
- Up to 2,800K logic elements
- For SX devices, Quad-core 64-bit ARM Cortex-A53 MPCore processor
- PCIe x16 Gen. 3 or stand-alone
- Up to 16× 25 Gb/s reconfigurable transceivers (total of 400 Gb/s)
- Form factor: full-height, double-width, ¾ length PCI Express card
- 4x QSFP28 or a combination of 2x QSFP28, 2x SFP28 and RGMII/Gidel proprietary
high-speed connector (PHS) - Multi-level memory structure (260+ GB):
- Enhanced MLAB (640-bit) SRAM (15 Mb)
- Up to 11,721 M20K (20K-bit) SRAM (229 Mb) at a maximum sustain throughput of 58 TB/s
- 4 GB DDR4 SDRAM on-board memory at a maximum sustained throughput of 13.5 GB/s
- 256 GB DDR4 SDRAM (2xRDIMM banks) at a maximum sustained throughput of 48 GB/s
- Configuration Flash, Serial Flash (SPI)
- SD Memory interface for SoC
- Maximum fabric clock frequency: 1 GHz
- Flexible clocking system
- Supported by Gidel’s Developer’s Kit
- Simultaneous acceleration of multiple applications or processes
- Unmatched HDL design productivity
- Simple integration with software applications
- Data management and data compression IPs
- Digital Signal Processing (DSP) and High Performance Reconfigurable Computing (HPRC)
- High Speed, Low-latency Networking and Network Analysis
- Life Science Applications
- Linear Algebra and 3D Applications
- Computational Finance and HFT
- Data Analytics
- Deep Packet Inspection
- Surveillance, Machine Vision, and Imaging
- High Performance Acquisition Systems
| Feature | Specification |
|---|---|
| FPGA | • Intel Stratix 10 GX and SX 2800/2100/1100 • Up to 2,800K logic elements • H-TILE supporting up to 16x 25 Gb/s SERDES I/O • For SX devices, Quad-core 64 bit ARM Cortex-A53 MPCore processor |
| Memory | • Embedded MLAB (640-bit) SRAM blocks • 11,721 M20K (20K-bit) SRAM blocks • Up to 256 GB DDR4 SDRAM SoDIMM with throughput of up to 13.5 GB/s • 4 GB on-board DDR4 SDRAM with throughput of up to 48 GB/s |
| Processing Performance | • Peak fixed-point performance 23.0 TMACS • Peak floating-point performance 9.2 TFLOPS • M20K blocks at up to 58 TB/s sustain access • Up to 11,520 18x19 variable precision multipliers • Up to 10x 25 Gb/s reconfigurable transceivers • Quad-core 64-bit ARM Cortex-A53 MPCore @ max processor speed of 1.5 GHz |
| Form Factor | Full-height, double-width, ¾ length PCI Express |
| Host Interface | PCIe x16 Gen.3 |
| I/O | 4x QSFP28 or a combination of 2xQSFP28, 2x SFP28 and RGMII/Gidel proprietary high-speed (PHS) connector. |
| Board Management | • Flexible clocking system • Temperature monitoring • Internal voltage monitoring • Support for Partial Reconfiguration and CvP |
| Development Tools | • Gidel ProcDev Kit for HDL design flow: o Generation of dedicated application driver o Splitting of physical on-board memories into logical memories with independent parallel access to/from user logic o Code generation for FPGA peripherals and interfaces • Intel Tools: Quartus Prime Pro, including QSys and DSP builder • HLS ASP for use with Intel’s HLS compiler |
Download our data sheet for Proc 10S Acceleration System.