Tools and IP

Gidel’s Developer’s Suite of tools optimizes system performance and reduces FPGA-based system development time.

The Developer’s Suite is based on more than 25 years of development and continuous improvement arising from valuable customer feedback. When used together with Intel’s design tools, the Developer’s Suite provides a market-unique solution that can achieve unmatched development productivity. The Gidel Developer’s Suite includes the following components:

  1. Proc Developer’s Kit (ProcDev Kit) provides an alternative to existing FPGA design methodologies and enables performance to be pushed to the limit. It is easy to use and automatically tailors the process of building the infrastructure required to support algorithm needs by optimizing the use of FPGAs, on-board memory resources, and FPGAs to host communication. The Developer’s kit includes the ProcWizard application, an API, examples, HDL and software libraries, and Gidel IPs.
  1. HLS Application Support Package (I++) enables the use of Intel’s High Level Synthesis (HLS) tool, which takes C++ as input and generates Register Transfer Level (RTL) optimized for FPGA. This tool accelerates the verification time over RTL by orders of magnitude and requires significantly fewer lines of code.

Key Features

  • HLS Application support package for compiling C++ to HDL — intended for algorithm and HDL designers
  • Gidel’s Developer’s Tools for efficient HDL design development:
    • Optimizes system performance
    • Simplifies HDL development tasks and integration with software
    • Automatically generates HDL envelope and respective software application drivers
    • Generates PCIe bridge and host interface
    • Debugging tool that directly accesses and controls the FPGA
    • Ability for multiple programs/processes to be accelerated concurrently on the same FPGA
    • Memory controller IPs

Key Benefits

  • Dramatically improves project development speed
  • Cuts development cycle time and budget while improving design reliability by enabling on-the-fly debugging
  • Simplifies the interaction between hardware and software developers
  • Easy maintenance — release a patch within a day
  • Automatically generated design documentation

Gidel Proc Developer’s Kit

Gidel Proc Developer’s Kit is a set of building blocks designed for maximum performance and fast, high-productivity system development. The kit includes the ProcWizard application, supporting libraries, and Gidel IPs.

ProcWizard Development Flow

The ProcWizard Application

Gidel ProcWizard™, included in the Proc Developer’s Kit, is a hardware–software integration application that simplifies project development tasks. Working in conjunction with Gidel FPGA boards, ProcWizard enables users to rapidly build a design that may be automatically translated into HDL and C++ code. The generated C++ code communicates with the generated HDL design via the PCI/e bus to ensure easy hardware–software integration.

In addition to code generation, the ProcWizard enables developers to test and debug designs in the PC environment. While in ProcWizard Debug Mode, designers can access the Proc board on-the-fly with a structural browser, manually or using macros/scripts.

Gidel ProcWizard enables hardware and software designers to work in parallel, sharing the same information and project definitions. This way, the time-to-market of project development may be greatly reduced and product reliability and maintenance may be improved.

ProcWizard’s main features include:

  • Automatic integration of software and hardware
  • Automatic integration of Gidel’s IP core into the design
  • HDL code generation
  • C++ application driver generation
  • Documentation generation
  • Hardware debugging

Gidel IPs

The Gidel Developer’s kit includes a set of IPs for simplifying and enhancing development tasks.

MultiPort IP

The MultiPort IP is a unique memory controller that optimizes on-board memory according to application data flow needs. This controller enables parallel access from up to 16 totally independent ports per memory bank. Each port may belong to a separate logical memory. All ports are connected to the same memory domain and can be accessed independently or simultaneously, with individual clock domains and data widths.


The MegaFIFO provides a simple and convenient way to transfer data between the acceleration board’s large memory banks and the FPGA logic and/or the host.

MegaDelay IP

The MegaDelay IP provides a convenient and effective method to create high-bandwidth large delays for optimized streaming applications. This IP, combined with the FPGA’s internal memory and logic, may significantly reduce memory access requirements.

Request Evaluation: ProcWizard Developer’s Software
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