Proc1C10N-CXP12:

Octo CoaXPress-12 Frame Grabber

8 x CXP-12 Frame grabber & Image Processing System

Up to 100 Gb/s bandwidth via 8 x CoaXPress-12 links
Ideal for AI, Recording & Streaming solutions
Inline FPGA image processing options include:
- Real-time detection for object, event, or feature identification
- On-FPGA real-time compression: JPEG, Lossless, Quality+
- Real-time High Dynamic Range (HDR) correction
Supports 100+ synchronized cameras using the InfiniVision
Memory: 8GB @ up to 300GB/s sustained throughput
Full-height, half-length PCB & bracket PCIe card (Gen. 3 x16)
Dual-slot

High-Performance Octo CXP-12 Frame Grabber

The Proc1C10N-CXP12 is a high-performance Octo CXP-12 Frame Grabber designed for real-time image acquisition, preprocessing, and compression in demanding multi-camera vision environments. Built on Gidel’s Proc10N FPGA module with Altera Stratix 10 NX FPGA technology, it integrates embedded Tensor blocks and HBM2 memory, delivering 143 INT8 TOPS / FP16 TFLOPS of processing power. As a result, it can process and analyze data from up to 8 × CXP-12 links, making it ideal for advanced vision-based AI systems.

Octo CXP-12 Acquisition with Real-Time FPGA Image Processing

The Proc1C10N-CXP12 is available as a plug-and-play CXP-12 frame grabber or as part of a complete Imaging & Vision system with real-time FPGA preprocessing, image enhancement, and compression options.

The built-in FPGA can process image data during acquisition, before it reaches the host PC. This helps reduce bandwidth, storage, and host processing load while preserving low-latency performance for high-speed camera streams.

Optional FPGA processing includes Compression, HDR correction, Detection, and additional image enhancement modules.

Real-Time FPGA Processing Helps Enable:

Reduced bandwidth for high-throughput image acquisition
Low-latency processing directly in the acquisition flow
Extended recording time through real-time compression
Lower host processing load by offloading selected tasks to the FPGA
Custom image pipelines using Gidel IPs or user FPGA logic

For the full list of available image processing and enhancement options, please refer to the Options tab.

Flexible Operating Modes

The Proc1C10N-CXP12 supports two operating modes selectable via firmware:

InfiniVision: Designed for synchronized multi-camera setups, combining all incoming data—even across multiple cards—into a single unified buffer with dynamic resolutions and formats.
ProcFG: Tailored for precision and line-scan applications, offering fixed frame sizes, pixel formats, and ROI grabbing (uncompressed).

As a result, the Proc1C10N-CXP12 adapts to diverse workflows—from complex multi-camera systems to single-camera applications requiring consistent, high-performance acquisition.

InfiniVision: Multi Camera Acquisition and Synchronization

Gidel’s InfiniVision architecture enables deterministic, synchronized acquisition from 100+ CXP-12 cameras. As a result, it manages bandwidth, connectivity, and scalability across large systems.
Meanwhile, a PCIe Gen3 x16 host interface ensures ultra-fast data transfer, and 8 x CXP-12 links provide up to 100 Gb/s aggregated bandwidth. In addition, on-board HBM2 and DDR4 memory sustain throughput even under extreme loads.

SDK and Development Tools

The Proc1C10N-CXP12 is supported by Gidel’s SDK, featuring intuitive GUIs and APIs for easy integration. Moreover, the ProcVision Suite adds advanced FPGA programming, debugging, and validation tools, enabling rapid customization of data pipelines, real-time processing, and compression workflows—so teams can deploy optimized, application-specific solutions faster and with reduced risk.

Why Choose the Proc1C10N-CXP12 Frame Grabber?

Octo CXP-12 FPGA frame grabber for high-speed multi-camera image acquisition
Up to 100 Gb/s aggregate input bandwidth
Embedded AI Tensor Blocks for acceleration and inference
Flexible operating modes for multi-camera and precision setups
Advanced SDK and ProcVision Suite for rapid development and integration
Optional real-time FPGA processing, image enhancement, and compression IPs

The Proc1C10N-CXP12 is the ideal choice when your workload requires high-bandwidth CXP-12 acquisition, deterministic multi-camera capture, and FPGA-based acceleration for AI-driven imaging workflows.

General

Supported Protocol

CoaXPress 2.1

Camera Input Options

Up to 8 x CoaXPress-12 links
PoCXP support

Camera Input Connectors

8 x Micro-BNC

Supported CXP Downlink Speeds

1.25 Gb/s | CXP-1
2.5 Gb/s | CXP-2
3.125 Gb/s | CXP-3
5 Gb/s | CXP-5
6.25 Gb/s | CXP-6
10 Gb/s | CXP-10
12.5 Gb/s | CXP-12

Supported CXP Uplink Speeds

20.83 Mbps (CXP-1 to CXP-6)
41.66 Mbps (CXP-10, CXP-12)

Maximum Stream Packet Size

8,192 bytes

Additional Connectors

Gidel PHS connector for daughterboards
JTAG

Advanced Features

On-the -fly selective ROI acquisition
Link Aggregation mode
Chunk Data

Image Formats

Mono, Bayer, RGBA (8, 10, 12, 14 and 16 bits/color)
RGB (8, 10 and 12 bits/color)

Max. Resolution

Horizontal: 16 K pixels (64-bit)
Vertical: 65 K lines

Maximum Acquisition Throughput

80Gb/s

Real-Time FPGA Image Compression

Supports optional FPGA-based compression options.
For the full list, please refer to the Options tab.

Compression & Image Enhancements

Compression Options:

Image Enhancements Options:

High Dynamic Range (HDR) correction

For more modular image-processing options - Contact Us

Real-Time FPGA Image Processing & Enhancements

Supports optional FPGA image processing and enhancement modules.
For the full list, please refer to the Options tab.

Host Bus

PCIe x 16 Gen. 3

On Board Memory

8GB @ up to 300GB/s Sustain Throughput

Camera Types

Area
Line Scan

Form Factor

Dual-slot, full-height half-length PCIe card

GPIO

GPIO #1:

12 x LVTTL IO (5V TTL tolerant)

GPIO #2:

2 x RS422 INPUTS
3 x Opto-coupler inputs
LVTTL IO
2 x 3-30V @ 0.8A outputs
12V/1A power supply

Power

Up to 100W: Depends on user application and FPGA Type

Cooling

Passive cooling
Active cooling (Fan)

MTBF

> Million hours (With Passive Cooling)

Environmental conditions

Temperature

Operating ambient air temperature: 0 – 55° C

Humidity

Continuous Operation: 10 - 80% (non-condensing)
Peak Operation: 10 - 90% (non-condensing)

Environmental Compliance

Real-Time FPGA Image Compression

Real-Time FPGA Image Processing & Enhancements

HDR Correction – High Dynamic Range correction from a single exposure
Detection – Enables real-time object, event, or feature detection at the acquisition stage
Chromatic Aberration Correction – Reduces color fringing caused by optical misalignment
Dynamic Luminance Balance – Preserves consistent brightness under changing illumination
White Balance – Maintains color accuracy across variable lighting conditions
NUC – Non-uniformity correction for improving sensor response consistency
BPR – Bad pixel replacement for correcting defective or unstable pixels
Morphological operations – Open/Close operations using a round structuring element

User FPGA code

Users can integrate their own FPGA code alongside Gidel IPs.

For more information, refer to the FPGA Processing tab

Carrier board

Option for user or Gidel custom carrier board
For customization services, contact Gidel

Camera Input

For configurations requiring more than 8 cameras, please contact us.

Memory Size

16GB @ up to 512GB/s Sustain Throughput

Acquisition Rate

Up to 200Gb/s

The Gidel Proc1C carrier board uses only one of the three Proc10N connectors. The two additional connectors available on the Proc10N board and can be used, per user design, for additional 400 Gb/s bandwidth, RDIMM interface and many additional I/Os.

The Proc1C10N-CXP12 Frame Grabber is a highly modular solution, designed to be tailored to meet unique application requirements.

Looking to adapt the Proc1C10N-CXP12 to match your vision?

Contact Our Experts

The Proc1C10N-CXP12 frame grabber offers two powerful customization paths to meet specific application requirements:

Pre-Configured FPGA Features
Gidel develops a range of pre-embedded modules tailored to your specifications, including real-time compression, image processing, and enhancement options.
For the full list of image processing and enhancements, please refer to the Options tab.
User-Level FPGA Customization
Leverage Gidel’s development tools and IP libraries to integrate your proprietary FPGA logic and extend the system’s capabilities for acquisition, image processing, and control.

The Gidel ProcVision Suite delivers a complete toolchain for advanced user-level FPGA customization of the data flow, image pipeline, image processing, and more, ensuring optimal performance for your vision or imaging application.

Gidel can also integrate customer algorithms into the FPGA or develop custom FPGA logic according to specific application requirements.

Proc1C10N FPGA Resources

Model	Proc1C10N-CXP12
FPGA	Stratix 10 NX (NX2100)
ALM	702,720
FPGA-MLAB	11Mb
FPGA-M20K	6,847
AI Tensor Blocks	3,960 AI Tensor Blocks; peak 143 INT8 TOPS / 286 INT4 TOPS
Peripheral Memory
eSRAM	94.5 Mb @ Max throughput of 90 GB/s
HBM2 DDR	Up to 16GB @ up to 512GB/s Sustain Throughput
DDR4 Capacity	Up to 128 GB with ECC
DDR4 max throughput	15 GB/s

Grabbers SDK

InfiniVision

Designed for acquisition from a large number of cameras (100+), with an option for embedded real-time compression.

ProcFG

Optimized for line-scan camera acquisition, combining ROI-based grabbing with integrated debugging and analysis tools.

Application Interfaces

GUI Applications

InfiniVision
ProcFG
CameraConfig – Camera discovery and configuration
ggvcon – GigE Vision network configuration

APIs

InfiniVision with supporting examples
ProcFG with supporting examples
Gen<i>Cam GenTL producer libraries compatible with C/C++ compilers
InitCam for developing user Gen<i>Cam camera configuration application
GigE for developing camera network communication applications

Software Compatibility

Third-party software

MVTec Halcon machine vision software
Camera control Gen<i>Cam based application

Operation Systems supported

Windows 11
Windows 10
Windows Server 2022
Windows Server 2019
Windows Server 2016
Linux (kernel 2.6.x- 6.12)

Please note: Linux version doesn’t include the ProcFG/InfiniVision GUI, just the API.

Name	Description	Type	Size
Proc1C10N-CXP12	Datasheet	PDF	290.4 KB
Proc1C10N-CXP12	Block Diagram	PNG	68.2 KB
Proc10N: Datasheet	FPGA module	PDF	194.4 KB
Proc10N: Block Diagram	FPGA module	JPG	73.9 KB
Proc1C: Datasheet	Carrier Board	PDF	133.5 KB
Proc1C: Block Diagram	Carrier Board	JPG	57.1 KB

Reuven Weintraub, founder and CTO of Gidel, reveals how to unlock exceptional image processing performance by adding FPGA’s processing at Vision Show, Stuttgart 2024.

Gidel frame grabbers and edge computers at the Embedded World show 2024.

Boost your vision! Gidel's high-performance GigE Vision, Camera Link and CoaXPress frame grabbers help overcome bandwidth bottlenecks in high-resolution and/or high-speed computer vision applications.

Gidel presented its FPGA-based architecture capable of processing Giga+ Pixels per second while maintaining exceptionally low power consumption. The session demonstrated how Gidel’s scalable FPGA solutions deliver real-time imaging performance, energy efficiency, and deterministic throughput for advanced vision and imaging systems.

Presented by Reuven Weintraub, this talk highlighted Gidel’s expertise in real-time processing over Gigapixel/s image streams, demonstrating how FPGA-based architectures enable deterministic latency, scalable throughput, and efficient handling of ultra–high-resolution vision data.

Gidel founder and CTO Reuven Weintraub present the performance and versatility of Gidel's GigE Vision, Camera Link and CoaXPress frame grabbers for high-speed image acquisition and pre-processing at the Embedded World 2022 in Nuremberg, Germany.

Gidel demonstrated a complete real-time object tracking pipeline implemented directly on the FPGA-based frame grabber, eliminating host dependency and overcoming PCIe bandwidth limitations. The demo showcased deterministic low-latency processing, highlighting Gidel’s ability to execute full vision workflows on FPGA hardware.

Gidel presented a step-by-step demonstration of its FPGA-based object tracking algorithm, highlighting the internal processing stages and real-time debugging capabilities. The demo illustrated how developers can visualize, analyze, and optimize the complete tracking flow directly on FPGA hardware, enabling faster development and deterministic performance.